1. Field of Use
This invention relates to memory systems containing memory elements in which information stored in the elements must be periodically refreshed or restored in order to preserve the integrity of such information. Such elements are normally termed volatile.
2. Prior Art
Apparatus which periodically restores information in volatile memory elements is well known. Normally, such apparatus restores information by either interleaving restoration with normal memory operations or in a burst mode by interrupting normal memory operations.
It has been noted that types of arrangements interfere with normal memory operation while restoration takes place. To eliminate such interference, one arrangement permits periodic restoration to be carried internally to the memory simultaneously with a normal memory access operation (i.e., read or write operation) and on a time ordered basis of previous restoration when no access to the memory is being made. To accomplish this, the array of memory elements is divided into a plurality of segments and the means for restoring information in the elements is actuated for a particular segment of the array each time an access to a portion of the array within that segment is made. The arrangement is disclosed in U.S. Pat. No. 3,811,117.
While the arrangement does not interfere with system operation in usual situations, there are times when it may not be possible to carry out all restore operations without disturbing normal memory operation. According to the patent, this arises when the memory system is accessing a few storage devices a high percentage of the cycle time intervals for the memory and accesses are being made to the memory in a high percentage of the access time intervals.
Another arrangement for refreshing memory elements of a memory containing a large number of rows makes use of refreshing cycles in parallel with a normal read-write memory operation. The memory array is divided into two blocks and when a central processing unit assigns a cycle for read-write operation to one block, the same cycle is utilized to refresh a row of memory elements of the other block. This arrangement is disclosed in U.S. patent application titled "Semiconductor Dynamic Memory and Related Refreshing System", Ser. No. 714,177, filed on Sept. 10, 1975 now U.S. Pat. No. 4,106,108 and assigned to Honeywell Information Systems Italia.
While the above arrangement reduces memory interference, there is a requirement for organizing the memory in a particular fashion which results in less flexibility and additional circuit complexity.
Additionally, because of the organizational constraints mentioned, the arrangements discussed above are not suitable for utilization in memory systems which include a plurality of modules for implementing a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation.
Accordingly, it is a primary object of the present invention to provide a memory system whose memory elements are refreshed with a minimum of interference to memory operations.
It is a further object of the present invention to provide apparatus for refreshing the memory elements of a plurality of modules of a memory system constructed to incorporate a double word fetch capability.